1. Field of the Invention
The present invention relates to a semiconductor memory device and more paticularly to a semiconductor memory device including a salicide layer (a metal silicide layer formed by self-alignment) formed on a gate electrode, source and drain regions.
2. Description of a Related Art
A semiconductor memory device such as a flash memory has a memory cell which has a gate electrode and source and drain regions. As the memory device is integrated, a memory cell is made fine, resulting in its gate resistance and source and drain resistance increasing. It prevents to enhancing the operation speed. A metal suicide layer is therefore formed on a gate electrode and source and drain regions to lower the gate resistance and source and drain resistance.
FIG. 12 and FIGS. 13A to 13C illustrate a so-called NOR type memory cell of a related art. FIG. 12 is a plane layout view of the memory cell. FIGS. 13A to 13C are cross-sectional views along the AA line, the BB line, and the CC line of FIG. 12.
Gate electrodes G are extended in the row direction (in the right and left direction of the Figure) and arranged at prescribed intervals in the column direction (in the up and down direction of the Figure). Each gate electrode G is composed of a control gate CG as a word line in the row direction and an island-like floating gate FG formed under the control gate CG and corresponding to respective memory cells.
Impurity diffusion layers 202, 203 as source regions S and drain regions D are reciprocally arranged between gate electrodes G in the column direction. The source regions S are formed continuously in parallel to the gate electrodes G in the row direction. The drain regions D are isolated by an element isolating insulation film 204 arranged at prescribed intervals in the row direction. A gate electrode G and a pair of a source region S and a drain region D sandwiching the gate electrode D constitute one memory cell MC.
In such a memory cell MC, in order to increase the operation speed as described above, a metal silicide layer 221 using a refractory metal such as cobalt, titanium or the like is formed on the surface of the control gate CG, and on the surface of the source region S and the drain region D to lower their resistance values. Metals 233 as a source contact electrode SC and a drain contact electrode DC in contact holes 232 opened in an interlayer insulation film 231 are connected to the source region S and the drain region D through the metal silicide layer 221. Each drain contact electrode DC is arranged in the drain region D of each memory cell MC. Each source contact electrode SC is arranged in a region with a widened width formed by bending some parts of the neighboring gate electrodes G in the longitudinal direction toward the mutually opposed directions in the column direction. Each drain contact electrode DC is connected with a bit line BL as a wiring 234 on the interlayer insulating film 231. Each source contact electrode SC is connected with a power source line VSS as a wiring 235.
The source regions S are continuously arranged in the row direction. The source regions S are formed by removing element isolating insulation films 204 formed for dielectric isolation of respective drain regions of memory cells MC in source formation area and implanting an impurity in the silicon substrate 201 to form a high concentration impurity diffusion layer 202 of the source regions S. As illustrated in FIG. 13B, the surface of the silicon substrate 201 in the source regions S has recessed parts 205 formed by removal of the element isolating insulation film 204 and consequently, the source regions S has a surface considerably made uneven by the recessed parts 205.
In case where there exist sharply recessed parts 205 in the surface of the source regions S as described above, when a metal silicide layer 221 is formed as described above to lower the resistance of gate electrodes G, source regions S and drain regions D, the resistance of the source and drain regions SD is sometimes contrary increased.
FIG. 14 shows an enlarged cross and plane views of some part of a recessed part 205 formed on the surface of a source region S. When an element isolating insulation film 204 formed by LOCOS method for selectively oxidizing surface of a silicon substrate 201 is removed by etching, a bird""s beak-like recessed part 205 with the depth of about 0.2 xcexcm is formed in the surface of a source region. Especially, in end parts of the recessed part 205, steeply inclined faces are formed. For that, when a refractory metal 220 is formed by a sputtering method to form the metal silicide layer 221 on the surface of the source region S, the coverage with the refractory metal 220 is deteriorated in the end parts of the recessed part 205. In that case, the refractory metal 220 is not formed with a sufficient film thickness to cause a siliciding reaction with the silicon in the source region S or is not at all formed in the end parts. Consequently, when siliciding reaction is carried out thereafter, no metal silicide layer 221 may be formed on the surface of the recessed part 205 of the source region S. Further, since the refractory metal 220 absorbs silicon atoms Si of the source region S at the time of siliciding reaction of the refractory metal 220, silicon atom is decreased in the to decrease the conductivity of the silicon. As a result, the electric resistance of the formed source region S is consequently increased. Incidentally, if the refractory metal 220 is formed to be thick, such a problem can be solved. However, the siliciding reaction of the refractory metal 220 and the silicon substrate 201 becomes excessive and a silicide layer is formed to be partially deeper than the depth of a diffusion layer. That results in impossibility of PN junction formation.
It is one of purpose of the invention is to lower the resistance of gate, source, drain, and source and drain contacts of a MOS type memory cell.
A semiconductor memory device of the present invention includes a plurality of non-volatile memory cells each having a source region, a source impurity diffusion layer divided into a first portion and a second portion extended from the first portion, a silicide layer formed on the second portion; and a source contact formed on the silicide layer. The first portion is the source regions of the memory cells so that no silicide film is formed on the first portion.
A semiconductor memory device of the present invention includes a first non-volatile memory cell having a first source region, a second non-volatile memory cell having a second source region, a source impurity diffusion layer divided into a first portion, a second portion and a third portion between the first and second portions, the first portion being the first source region and the second portion being the second source region, a silicide layer formed on the third portion and not formed on the first and second portions, and a source contact connected to said third portiong through said silicide layer.
A semiconductor memory device of the present invention includes a semiconductor substrate having a plurality of projected and recessed parts in the surface, a source region continuously formed on the projected and recessed parts of the semiconductor substrate to cover the projected and recessed parts, the source region running in a first direcion, an interlayer insulation film having an opening exposing a part of the surface of the source region so that no silicide layer is formed between the interlayer insulating film and the source region without the opening, and
a metal silicide layer covering the opening of the source region.
In a semiconductor memory device of the invention, even if projected and recessed parts exist in the surface of source regions, since no metal silicide layer is formed on the projected and recessed parts, the metal silicide layer is not formed in disconnected state in the projected and recessed parts and the metal for forming the metal silicide layer does also not absorb silicon atom of the source regions to prevent increase of the electric resistance of the source regions. Further, on the other hand, since the metal silicide layer is formed in the regions where source contact electrodes are to be formed, the source contact resistance can be lowered.
Further, a fabrication method of a semiconductor memory device of the invention includes forming gate electrodes in the surface of a semiconductor substrate, forming source and drain regions in both sides of the gate electrodes, forming side walls by the side faces of the gate electrodes, and forming a metal silicide layer. In the step of forming the side walls, first side walls are formed on side faces of the gate electrodes and second side walls are formed with an insulatinfg film on the first side walls to expose said drain region and to cover source regions other than a source contact formation region.
According to the fabrication method of the invention, the source regions are buried with the insulation film by simply carrying out forming side walls only two times. It is made possible to easily fabricate a semiconductor memory device having no metal silicide layer in the source regions by a salicide formation step. Further, in the case of simultaneously forming memory cells and the peripheral circuits, if a side wall is formed only for the memory cells at the first time, the simultaneous formation can be performed by covering only the surface of the source regions with an insulation film by forming side walls at the second time simultaneously with the peripheral circuits after then. Consequently, only adding the step of forming the side walls only one time for the memory cells to the fabrication process of such a type of semiconductor memory device, a semiconductor memory device of the invention can easily be fabricated without changing the fabrication steps of a related method.
Incidentally, Japanese Patent Laid-Open No. 2000-243935 discloses a non-volatile semiconductor memory device in which no silicide layer is formed in source regions and a silicide layer is formed in drain regions. The drain regions has a low impurity concentration to form a Schottoky contact with a metal a metal silicide layer. The non-volatile semiconductor memory device has a structure where carriers transmitted through the Schottoky barrier are accelerated in an electric field applied to the metal silicide layer and injected and accumulated in floating gates.